Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR gates. Separate output control inputs are provided for each of the two four-line sections.
The three-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state) the low-impedance of the single enabled output will drive the bus line to a high or low logic level.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | Dual 4-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs datasheet | Mar 1, 1988 | |
| * | SMD | SN54LS253 SMD 76017012A | Jun 21, 2016 |
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