Packaging information
| Package | Pins CDIP (J) | 14 |
| Operating temperature range (°C) -55 to 125 |
| Package qty | Carrier 25 | TUBE |
Features for the SN54LS91
- For applications in:
- Digital Computer Systems
- Data-Handling Systems
- Control Systems
| TYPE
|
TYPICAL
MAXIMUM CLOCK FREQUENCY |
TYPICAL
POWER DISSIPATION | |||
|---|---|---|---|---|---|
Description for the SN54LS91
These monolithic serial-in, serial-out, 8-bit shift registers utilize transistor-transistor logic (TTL) circuits and are composed of eight R-S master-slave flip-flops, input gating, and a clock driver. Single-rail data and input control are gated through inputs A and B and an interanl inverter to form the complementary inputs to the first bit of the shift register. Drive for the internal common clock line is provided by an inverting clock driver. This clock pulse inverter/driver causes these circuits to shift information one bit on the positive edge of an input clock pulse.