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SN74AHC165-Q1

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Automotive 4.5-V to 5.5-V 8-bit parallel-load shift register

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Data sheet

SN74AHC165-Q1

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Product details

Technology family AHC Input type Standard CMOS Output type 3-State Features Balanced outputs, Output register, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Automotive
Technology family AHC Input type Standard CMOS Output type 3-State Features Balanced outputs, Output register, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Automotive
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) WQFN (BQB) 16 8.75 mm² (3.5 mm × 2.5 mm)
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN (WBQA) package
  • Operating range 2-V to 5.5-V V CC
  • Low delay, 6 ns (25 °C, 5 V)
  • Latch-up performance exceeds 250 mA per JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN (WBQA) package
  • Operating range 2-V to 5.5-V V CC
  • Low delay, 6 ns (25 °C, 5 V)
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74AHC165-Q1 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state.

The SN74AHC165-Q1 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state.
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* Data sheet SN74AHC165-Q1 Automotive 8-Bit Shift Registers With 3-State Output Registers datasheet PDF | HTML Nov 17, 2023

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TSSOP (PW) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian
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