The SN74AHC573 is an octal transparent D-type latch designed for 2-V to 5.5-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
|Part number||Order||Technology Family||Input type||Output type||VCC (Min) (V)||VCC (Max) (V)||IOL (Max) (mA)||IOH (Max) (mA)||Rating||Package Group|
CDIP | 20
CFP | 20
LCCC | 20
PDIP | 20
SOIC | 20
SO | 20
SSOP | 20
TSSOP | 20
TVSOP | 20