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SN74AHCT16373

ACTIVE

16-Bit Transparent D-Type Latches With 3-State Outputs

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Data sheet

SN74AHCT16373

ACTIVE
Data sheet Order now

Product details

Number of channels 16 Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 110 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Flow-through pinout, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 16 Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 110 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Flow-through pinout, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Members of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Process
  • Inputs are TTL-Voltage Compatible
  • Distributed VCC and GND Pins Minimize High-Speed
    Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883,
    Method 3015; Exceeds 200 V Using Machine Model
    (C = 200 pF, R = 0)
  • Package Options Include:
    • Plastic Shrink Small-Outline (DL) Package
    • Thin Shrink Small-Outline (DGG) Package
    • Thin Very Small-Outline (DGV) Package
    • 80-mil Fine-Pitch Ceramic Flat (WD) Package
      Using 25-mil Center-to-Center Spacings
  • Members of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Process
  • Inputs are TTL-Voltage Compatible
  • Distributed VCC and GND Pins Minimize High-Speed
    Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883,
    Method 3015; Exceeds 200 V Using Machine Model
    (C = 200 pF, R = 0)
  • Package Options Include:
    • Plastic Shrink Small-Outline (DL) Package
    • Thin Shrink Small-Outline (DGG) Package
    • Thin Very Small-Outline (DGV) Package
    • 80-mil Fine-Pitch Ceramic Flat (WD) Package
      Using 25-mil Center-to-Center Spacings

The SNxAHCT16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The SNxAHCT16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
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Technical documentation

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Type Title Date
* Data sheet SNx4AHCT16373 16-Bit Transparent D-Type Latches With 3-State Outputs datasheet (Rev. I) PDF | HTML 05 Aug 2014
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

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SSOP (DL) 48 View options
TSSOP (DGG) 48 View options
TVSOP (DGV) 48 View options
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