SN74AHCT164-Q1

ACTIVE

Automotive, 4.5-V to 5.5-V 8-bit, parallel-out serial shift registers

SN74AHCT164-Q1

ACTIVE

Product details

Configuration Serial-in Bits (#) 8 Technology family AHCT Input type TTL-Compatible CMOS Output type 3-State IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Automotive
Configuration Serial-in Bits (#) 8 Technology family AHCT Input type TTL-Compatible CMOS Output type 3-State IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Automotive
TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm)
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 14ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 14ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17

The SN74AHCT164-Q1 is an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Outputs are directly connected to the internal shift register, resulting in immediate output changes as values are shifted into the register. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The SN74AHCT164-Q1 is an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Outputs are directly connected to the internal shift register, resulting in immediate output changes as values are shifted into the register. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

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* Data sheet SN74AHCT164-Q1 Automotive 8-Bit Parallel-Out Serial Shift Register datasheet PDF | HTML Mar 27, 2024

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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TSSOP (PW) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian

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