SN74AHCT1G125

ACTIVE

Single 4.5-V to 5.5-V buffer with TTL-compatible CMOS inputs and 3-state outputs

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Single 4.5-V to 5.5-V buffer with TTL-compatible CMOS inputs and 3-state outputs

SN74AHCT1G125

ACTIVE

Product details

Parameters

Technology Family AHCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 IOL (Max) (mA) 8 ICC (Max) (uA) 10 IOH (Max) (mA) -8 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 5 2 mm² 1.65 x 1.2 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1 open-in-new Find other Non-Inverting buffer/driver

Features

  • Operating Range of 4.5 V to 5.5 V
  • Max tpd of 6 ns at 5 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 5 V
  • Inputs are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
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Description

The SN74AHCT1G125 device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, data is passed from the A input to the Y output.

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Technical documentation

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Type Title Date
* Data sheet SN74AHCT1G125 Single Bus Buffer Gate With 3-State Output datasheet (Rev. N) Feb. 01, 2016
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) Dec. 02, 2002
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guide AHC/AHCT Designer's Guide February 2000 (Rev. D) Feb. 24, 2000
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) Apr. 01, 1998
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) Apr. 01, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCLJ016.ZIP (85 KB) - HSpice Model
SIMULATION MODEL Download
SCLM018.ZIP (7 KB) - IBIS Model
SIMULATION MODEL Download
SCLM245.ZIP (7 KB) - PSpice Model
SIMULATION MODEL Download
SCYM002.ZIP (21 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SC70 (DCK) 5 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options

Ordering & quality

Information included:
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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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