The SN74AHCT273-Q1 contains eight positive-edge-triggered D-type flip-flops with a direct active low clear ( CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SN74AHCT273-Q1 Automotive Octal D-Type Flip-Flops with Clear datasheet | PDF | HTML | Jul 6, 2025 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
| VSSOP (DGS) | 20 | Ultra Librarian |
| VQFN (RKS) | 20 | Ultra Librarian |
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