The SN74AHCT373-Q1 contains eight D-type latches. All channels share a latch enable (LE) input and output enable (OE) input.
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SN74AHCT373-Q1 Automotive Octal Transparent D-Type Latches with 3-State Outputs datasheet | PDF | HTML | Jul 6, 2025 |
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The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
| VQFN (RKS) | 20 | Ultra Librarian |
| VSSOP (DGS) | 20 | Ultra Librarian |
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