Product details

Technology Family ALS IOL (Max) (mA) 24 IOH (Max) (mA) -15 Operating temperature range (C) 0 to 70 Rating Catalog
Technology Family ALS IOL (Max) (mA) 24 IOH (Max) (mA) -15 Operating temperature range (C) 0 to 70 Rating Catalog
PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2
  • 4.5-V to 5.5-V VCC Operation
  • Max tpd of 5.5 ns at 5 V
  • 3-State Outputs Drive Bus Lines Directly
  • pnp Inputs Reduce dc Loading

  • 4.5-V to 5.5-V VCC Operation
  • Max tpd of 5.5 ns at 5 V
  • 3-State Outputs Drive Bus Lines Directly
  • pnp Inputs Reduce dc Loading

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated.

The -1 version of the SN74ALS245A is identical to the standard version, except that the recommended maximum IOL is increased to 48 mA. There is no -1 version of the SN54ALS245A.

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated.

The -1 version of the SN74ALS245A is identical to the standard version, except that the recommended maximum IOL is increased to 48 mA. There is no -1 version of the SN54ALS245A.

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Technical documentation

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Type Title Date
* Data sheet SN54ALS245A, SN54AS245, SN74ALS245A, SN74AS245 datasheet (Rev. A) 13 Jan 2003
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Advanced Schottky (ALS and AS) Logic Families 01 Aug 1995

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, P, N, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
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Limit: 5
Simulation model

SN74ALS245A IBIS Model (Rev. B)

SDAM018B.ZIP (7 KB) - IBIS Model
Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options

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