SN74ALVC126

ACTIVE

Quadruple Bus Buffer Gate With 3-State Outputs

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Product details

Parameters

Technology Family ALVC VCC (Min) (V) 1.65 VCC (Max) (V) 3.6 Channels (#) 4 IOL (Max) (mA) 24 ICC (Max) (uA) 10 IOH (Max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Data rate (Mbps) 200 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 open-in-new Find other Non-Inverting buffer/driver

Features

  • Operates From 1.65 V to 3.6 V
  • Max tpd of 3.1 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN74ALVC126 datasheet (Rev. J) Sep. 17, 2004
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guides ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) Aug. 01, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
Application notes TI SN74ALVC16835 Component Specification Analysis for PC100 Aug. 03, 1998
Application notes Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) May 13, 1998
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCEJ217.ZIP (97 KB) - HSpice Model
SIMULATION MODELS Download
SCEM246.ZIP (45 KB) - IBIS Model
SIMULATION MODELS Download
SCEM764.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SO (NS) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options

Ordering & quality

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