SN74ALVC16835

ACTIVE

18-Bit Universal Bus Driver With 3-State Outputs

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18-Bit Universal Bus Driver With 3-State Outputs

SN74ALVC16835

ACTIVE

Product details

Parameters

Technology Family ALVC VCC (Min) (V) 1.65 VCC (Max) (V) 3.6 Channels (#) 18 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (uA) 40 Input type Standard CMOS Output type 3-State Features Balanced Outputs, Ultra high speed (tpd <5ns), Over-voltage tolerant inputs Data rate (Max) (Mbps) 300 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Universal bus driver (UBD)

Package | Pins | Size

SSOP (DL) 56 191 mm² 18.42 x 10.35 TSSOP (DGG) 56 113 mm² 14 x 8.1 open-in-new Find other Universal bus driver (UBD)

Features

  • Member of the Texas Instruments Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 2 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Ideal for Use in PC100 Register DIMM Revision 1.1
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

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Description

This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN74ALVC16835 datasheet (Rev. J) Oct. 20, 2004
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guides ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) Aug. 01, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
Application notes TI SN74ALVC16835 Component Specification Analysis for PC100 Aug. 03, 1998
Application notes Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) May 13, 1998
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODELS Download
SCEM040A.ZIP (12 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SSOP (DL) 56 View options
TSSOP (DGG) 56 View options

Ordering & quality

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