SN74ALVCH162334

ACTIVE

16-Bit Universal Bus Driver With 3-State Outputs

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16-Bit Universal Bus Driver With 3-State Outputs

SN74ALVCH162334

ACTIVE

Product details

Parameters

Technology Family ALVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 3.6 Number of channels (#) 16 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Input type Standard CMOS Output type 3-State Features Balanced outputs, Ultra high speed (tpd <5ns), Over-voltage tolerant inputs, Damping resistors, Bus-hold Data rate (Max) (Mbps) 300 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Universal bus driver (UBD)

Package | Pins | Size

SSOP (DL) 48 164 mm² 15.88 x 10.35 TSSOP (DGG) 48 101 mm² 12.5 x 8.1 TVSOP (DGV) 48 62 mm² 9.7 x 6.4 open-in-new Find other Universal bus driver (UBD)

Features

  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
  • Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages

NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.

Widebus, EPIC are trademarks of Texas Instruments.

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Description

This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162334 is characterized for operation from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet SN74ALVCH162334 datasheet (Rev. H) Aug. 24, 2004
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) Sep. 17, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) Aug. 01, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 Aug. 03, 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) May 13, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODEL Download
SCEM066A.ZIP (10 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SSOP (DL) 48 View options
TSSOP (DGG) 48 View options
TVSOP (DGV) 48 View options

Ordering & quality

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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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