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This 10-bit flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The flip-flops of the SN74ALVCH16820 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.
A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or undriven inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SN74ALVCH16820 datasheet (Rev. G) | Sep 16, 2004 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | Dec 15, 2022 | |
| Application note | An Overview of Bus-Hold Circuit and the Applications (Rev. B) | Sep 17, 2018 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
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