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Noninverting buffers & drivers

SN74AUC16244

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16-ch, 0.8-V to 2.7-V high speed buffers with 3-state outputs

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Data sheet

SN74AUC16244

ACTIVE
Data sheet Order now

Product details

Technology family AUC Number of channels 16 IOL (max) (mA) 9 Supply current (max) (µA) 20 IOH (max) (mA) -9 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUC Number of channels 16 IOL (max) (mA) 9 Supply current (max) (µA) 20 IOH (max) (mA) -9 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm) TVSOP (DGV) 48 62.08 mm² (9.7 mm × 6.4 mm)
  • Member of the Texas Instruments Widebus Family
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 2 ns at 1.8 V
  • Low Power Consumption, 20-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus Is a trademark of Texas Instruments
  • Member of the Texas Instruments Widebus Family
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 2 ns at 1.8 V
  • Low Power Consumption, 20-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus Is a trademark of Texas Instruments

This 16-bit buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC16244 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This 16-bit buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC16244 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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SN74ALVCH16244 ACTIVE 16-ch, 1.65-V to 3.6-V buffers with bus-hold and 3-state outputs Voltage range 1.65V to 3.6V, average propagation delay 3ns, average drive strength 24mA

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 16-Bit Buffer/Driver With 3-State Outputs datasheet (Rev. E) Feb 28, 2008
Application note Simultaneous-Switching Performance of TI Logic Devices (Rev. B) Feb 23, 2005
Application note Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices Mar 21, 2003

Design & development

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Simulation model

HSPICE Model for SN74AUC16244

SCEM536.ZIP (113 KB) - HSpice model
Supported products & hardware
Simulation model

SN74AUC16244 Behavioral SPICE Model

SCEM733.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74AUC16244 IBIS Model

SCEM312.ZIP (72 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
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