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8-Bit Dual-Supply Bus Transceiver

SN74AXCH8T245

ACTIVE

Product details

Parameters

Technology Family AXC Applications RGMII Bits (#) 8 High input voltage (Min) (Vih) 0.455 High input voltage (Max) (Vih) 3.6 Output voltage (Min) (V) 0.65 Output voltage (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog open-in-new Find other Direction-controlled voltage translators

Package | Pins | Size

TSSOP (PW) 24 34 mm² 7.7 x 4.4 VQFN (RHL) 24 19 mm² 5.5 x 3.5 open-in-new Find other Direction-controlled voltage translators

Features

  • Qualified Fully Configurable Dual-Rail Design Allows Each Port to Operate With a Power Supply Range From 0.65 V to 3.6 V
  • Operating Temperature From –40°C to +125°C
  • Bus-hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
  • Multiple Direction Control Pins to Allow Simultaneous Up and Down Translation
  • Up to 380 Mbps support when translating from 1.8 V to 3.3 V
  • VCC Isolation Feature to Effectively Isolate Both Buses in a Power-Down Scenario
  • Partial Power-Down Mode to Limit Backflow Current in a Power-Down Scenario
  • Compatible With SN74AVCH8T245 and 74AVCH8T245 Level Shifters
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model
    • 1000-V Charged-Device Model

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Description

The SN74AXCH8T245 device is an 8-bit non-inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, 3.3 V) and vice versa.

The device operates by using two independent power-supply rails (VCCA and VCCB) . Data pins A1 through A8 are designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track VCCB, which accepts any supply voltage from 0.65 V to 3.6 V. Additionally the SN74AXCH8T245 is compatible with a single-supply system.

The SN74AXCH8T245 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable (OE) input is used to disable the outputs so the buses are effectively isolated.

The SN74AXCH8T245 device is designed so the control pins (DIR and OE) are referenced to VCCA.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pull-up or pull-down resistors with the bus-hold circuitry is not recommended. If a supply is present for VCCA or VCCB, the bus-hold circuitry always remains active on all A and B ports respectively, independent of the direction control or output enable.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The VCC isolation feature ensures that if either VCC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state. To ensure the high-impedance state of the level shifter I/Os during power up or power down, OE should be tied to VCCA through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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SN74AVCH24T245 ACTIVE 24-bit dual-supply bus transceiver with configurable voltage translation and 3-state outputs Similar function in 24-channel version

Technical documentation

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Type Title Date
* Datasheet SN74AXCH8T245 8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Circuitry datasheet (Rev. A) Jan. 07, 2019
Application note Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. A) Apr. 02, 2019
User guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. A) Feb. 18, 2019
Application note Glitch free power sequencing with AXC level translators (Rev. A) Sep. 20, 2018
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) Sep. 17, 2018
User guide SN74AXC8T245 Evaluation Module Aug. 02, 2017
User guide Generic AVC and LVC Direction Controlled Translation EVM May 09, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARD Download
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor
EVALUATION BOARD Download
20
Description

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC is (...)

Features
  • SMB connector available for high speed operation
  • Ground port available on each header pin to maintain signal integrity
  • DIR and OE have 10K ohm pull up /pull down resistor options
  • Designed to support up to 20 different devices
EVALUATION BOARD Download
20
Description
This EVM is designed to support SN74AXC8T245 which is an 8 channel direction-controlled translation device. There is also option of populating 1, 2, 4 channel LVC and AVC direction controlled translation device. It also supports the bus hold and Q1 devices in the same number of channels. The AXC (...)
Features
  • High speed SMB connector available
  • Gnd port for each header pin supports high speed measurement
  • DIR and OE pin have 10K ohm pulldown built in
  • Layout optimized for high speed connectivity
  • Device supports 2 DIR pins each controlling  4 channel bank

Design tools & simulation

SIMULATION MODEL Download
SCEM583A.ZIP (29 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 24 View options
VQFN (RHL) 24 View options

Ordering & quality

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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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