SN74CBTU4411

ACTIVE

Product details

Protocols DDR2 Configuration 4:1 Number of channels 11 Bandwidth (MHz) 400 Supply voltage (max) (V) 1.9 Supply voltage (min) (V) 1.7 Ron (typ) (mΩ) 10000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 1.9 Supply current (typ) (µA) 700 ESD HBM (typ) (kV) 2.5 Operating temperature range (°C) 0 to 85 ESD CDM (kV) 0.75 Input/output continuous current (max) (mA) 100 COFF (typ) (pF) 2.5 CON (typ) (pF) 4.6 OFF-state leakage current (max) (µA) 10 Propagation delay time (µs) 0.000297 Ron (max) (mΩ) 17000 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 2.1 Turnon time (enable) (max) (ns) 2.1 VIH (min) (V) 1.1 VIL (max) (V) 0.66
Protocols DDR2 Configuration 4:1 Number of channels 11 Bandwidth (MHz) 400 Supply voltage (max) (V) 1.9 Supply voltage (min) (V) 1.7 Ron (typ) (mΩ) 10000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 1.9 Supply current (typ) (µA) 700 ESD HBM (typ) (kV) 2.5 Operating temperature range (°C) 0 to 85 ESD CDM (kV) 0.75 Input/output continuous current (max) (mA) 100 COFF (typ) (pF) 2.5 CON (typ) (pF) 4.6 OFF-state leakage current (max) (µA) 10 Propagation delay time (µs) 0.000297 Ron (max) (mΩ) 17000 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 2.1 Turnon time (enable) (max) (ns) 2.1 VIH (min) (V) 1.1 VIL (max) (V) 0.66
NFBGA (ZST) 72 49 mm² 7 x 7
  • Supports SSTL_18 signaling levels
  • Suitable for DDR-II applications
  • D-port outputs are precharged by bias voltage (VBIAS)
  • Internal termination for control inputs
  • High bandwidth (400 MHz minimum)
  • Low and flat ON-state resistance (ron) characteristics, (ron = 17 Ω maximum)
  • Internal 400-Ω pulldown resistors
  • Low differential and rising or falling edge skew
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • Supports SSTL_18 signaling levels
  • Suitable for DDR-II applications
  • D-port outputs are precharged by bias voltage (VBIAS)
  • Internal termination for control inputs
  • High bandwidth (400 MHz minimum)
  • Low and flat ON-state resistance (ron) characteristics, (ron = 17 Ω maximum)
  • Internal 400-Ω pulldown resistors
  • Low differential and rising or falling edge skew
  • Latch-up performance exceeds 100 mA per JESD 78, Class II

The SN74CBTU4411 device is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (ron). The device uses an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ron. The low and flat ron allows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ron and I/O capacitance among channels results in extremely low differential and rising or falling edge skew. This allows the device to show optimal performance in DDR-II applications.

The SN74CBTU4411 device is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (ron). The device uses an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ron. The low and flat ron allows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ron and I/O capacitance among channels results in extremely low differential and rising or falling edge skew. This allows the device to show optimal performance in DDR-II applications.

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Technical documentation

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Type Title Date
* Data sheet SN74CBTU4411 11-Bit 1-of-4 Multiplexer or Demultiplexer 1.8-V DDR-II Switch With Charge Pump and Precharged Outputs datasheet (Rev. C) PDF | HTML 13 Sep 2021
Application brief 1.8-V Logic for Multiplexers and Signal Switches (Rev. C) PDF | HTML 26 Jul 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Digital Bus Switch Selection Guide (Rev. A) 10 Nov 2004
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature CBT RAID Application Clip 12 Jun 2003
Application note Bus FET Switch Solutions for Live Insertion Applications 07 Feb 2003
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Flexible Voltage-Level Translation With CBT Family Devices 20 Jul 1999
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 01 Dec 1998
Application note 3.3-V to 2.5-V Translation with Texas Instruments Crossbar Technology (Rev. A) 03 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note 5-V To 3.3-V Translation With the SN74CBTD3384 (Rev. B) 01 Mar 1997
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Simulation model

HSPICE Model for SN74CBTU4411

SCDJ034.ZIP (101 KB) - HSpice Model
Simulation model

SN74CBTU4411 IBIS Model

SCDM101.ZIP (75 KB) - IBIS Model
Package Pins CAD symbols, footprints & 3D models
NFBGA (ZST) 72 Ultra Librarian

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