This device contains four independent 2-input NAND Gates. Each gate performs the Boolean function Y = A ● B in positive logic.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SNx4HC00 Quadruple 2-Input NAND Gates datasheet (Rev. H) | PDF | HTML | Sep 14, 2021 |
| Application brief | Using Linear Interpolation to Estimate Specification Values | PDF | HTML | Apr 13, 2026 | |
| Technical article | How to latch off a power converter that has a hiccup fault response | PDF | HTML | Dec 20, 2023 | |
| Application note | Optimizing Asset Tracking Systems With Logic and Translation Use Cases | PDF | HTML | Apr 12, 2021 | |
| Application brief | SIM Voltage Translation | PDF | HTML | Apr 5, 2021 | |
| Application note | Optimizing Design of Smart Thermostats with Logic and Translation Use Cases (Rev. A) | PDF | HTML | Apr 1, 2021 | |
| Application note | Optimizing AC Drive Control Panel Systems With Logic and Translation Use Cases | Jan 20, 2021 | ||
| Application note | Optimizing Design of Electronic Meters with Logic and Translation Use Cases | Jun 2, 2020 | ||
| Technical article | It’s all in the family: a brief guide to logic family selection | PDF | HTML | Sep 10, 2015 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| SSOP (DB) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
| PDIP (N) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
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