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SN74HCS03

ACTIVE

Schmitt-trigger inputs quadruple 2-input positive-NAND gates with open-drain outputs

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Data sheet

SN74HCS03

ACTIVE
Data sheet Order now

Product details

Technology family HCS Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Input type Schmitt-Trigger Output type Open-drain Features High speed (tpd 10-50ns) Data rate (max) (Mbps) 130 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family HCS Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Input type Schmitt-Trigger Output type Open-drain Features High speed (tpd 10-50ns) Data rate (max) (Mbps) 130 Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 5 V
  • Extended ambient temperature range: –40°C to +125°C, TA
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 5 V
  • Extended ambient temperature range: –40°C to +125°C, TA

This device contains four independent 2-input NAND gates with open-drain outputs and Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic.

This device contains four independent 2-input NAND gates with open-drain outputs and Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic.
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Technical documentation

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Type Title Date
* Data sheet SN74HCS03 Quadruple 2-Input Positive-NAND Gates datasheet (Rev. A) 22 Oct 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
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Simulation model

SN74HCS03 Behavioral SPICE Model

SCLM304.ZIP (10 KB) - PSpice Model
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Simulation model

SN74HCS03 IBIS Model

SCLM167.ZIP (162 KB) - IBIS Model
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Package Pins Download
SOIC (D) 14 View options
TSSOP (PW) 14 View options
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