High speed CMOS logic 3-to-8 line decoder demultiplexer with address latches
Product details
Parameters
Package | Pins | Size
Features
- Wide operating voltage range: 2 V to 6 V
- Schmitt-trigger inputs allow for slow or noisy input signals
- Low power consumption
- Typical ICC of 100 nA
- Typical input leakage current of ±100 nA
- ±7.8-mA output drive at 6 V
- Extended ambient temperature range: –40°C to +125°C, TA
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Description
The SN74HCS237 is a three to eight decoder with latched address inputs, one standard output strobe (G0), and one active low output strobe (G 1). When the latch enable (LE) input is high, the device acts as a standard three to eight decoder. When the latch enable (LE) input is low, the address latch retains its previous state. When the outputs are gated by either strobe input, they are all forced into the low state. When the outputs are not disabled by one or both of the strobe inputs, only the selected output is high while all others are low.
功能和引脚相同,但与相比较的设备不等效:
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | SN74HCS237 3- to 8-Line Decoder/Demultiplexer with Address Latches datasheet | Sep. 10, 2020 |
Design & development
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Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Design tools & simulation
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 16 | View options |
TSSOP (PW) | 16 | View options |
Ordering & quality
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Support & training
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