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SN74LV04A

ACTIVE

6-ch, 2-V to 5.5-V inverters

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Data sheet

SN74LV04A

ACTIVE
Data sheet Order now

Product details

Technology family LV-A Number of channels 6 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Number of channels 6 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
TVSOP (DGV) 14 23.04 mm² (3.6 mm × 6.4 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) VQFN (RGY) 14 12.25 mm² (3.5 mm × 3.5 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm)
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down Mode
    Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down Mode
    Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model

This hex inverter is designed for 2-V to 5.5-V VCC operation. The SN74LV04A device contains six independent inverters. This device perform the Boolean function Y = A.

This hex inverter is designed for 2-V to 5.5-V VCC operation. The SN74LV04A device contains six independent inverters. This device perform the Boolean function Y = A.
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Technical documentation

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* Data sheet SN74LV04A Hex Inverters datasheet (Rev. K) PDF | HTML Dec 21, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
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Simulation model

HSPICE Model of SN74LV04A

SCEJ149.ZIP (30 KB) - HSpice model
Supported products & hardware
Simulation model

SN74LV04A Behavioral SPICE Model

SCLM193.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74LV04A IBIS Model

SCEM105.ZIP (6 KB) - IBIS model
Supported products & hardware
Simulation model

SN74LV04A IBIS Model (Rev. A)

SCEM104 (7 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TVSOP (DGV) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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