SN74LV125A-Q1

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Automotve catalog quadruple bus buffer gates with 3-state outputs

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Automotve catalog quadruple bus buffer gates with 3-state outputs

SN74LV125A-Q1

ACTIVE

Product details

Parameters

Technology Family LV-A VCC (Min) (V) 2 VCC (Max) (V) 5.5 Channels (#) 4 IOL (Max) (mA) 16 ICC (Max) (uA) 20 IOH (Max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Data rate (Mbps) 220 Rating Automotive open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other Non-Inverting buffer/driver

Features

  • Qualified for Automotive Applications
  • 2-V to 5.5-V VCC Operation
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation

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Description

The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.

This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN74LV125A-Q1, Quadruple Bus Buffer Gates With 3-State Outputs datasheet Oct. 01, 2010
More literature Automotive Logic Devices Brochure Aug. 27, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODEL Download
SCEM657.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
VQFN (RGY) 14 View options

Ordering & quality

Information included:
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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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