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SN74LV8T541-Q1

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Automotive eight-bit fixed-direction level translator with tri-state outputs

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Data sheet

SN74LV8T541-Q1

ACTIVE
Data sheet Order now

Product details

Bits (#) 8 Data rate (max) (Mbps) 150 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Single supply, Wettable flanks package Prop delay (ns) 13.7 Technology family LVxT Supply current (max) (mA) 1.5 Rating Automotive Operating temperature range (°C) -40 to 125
Bits (#) 8 Data rate (max) (Mbps) 150 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Single supply, Wettable flanks package Prop delay (ns) 13.7 Technology family LVxT Supply current (max) (mA) 1.5 Rating Automotive Operating temperature range (°C) -40 to 125
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 VQFN (RKS) 20 11.25 mm² 4.5 x 2.5 VSSOP (DGS) 20 24.99 mm² 5.1 x 4.9
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B

  • Available in Wettable Flanks QFN package

  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B

  • Available in Wettable Flanks QFN package

  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17

The SN74LV8T541-Q1 contains eight non-inverting buffers with 3-state outputs. The active low output enable pins (/OE1 and /OE2) control all eight channels, and are configured so that both must be low for the outputs to be active.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The SN74LV8T541-Q1 contains eight non-inverting buffers with 3-state outputs. The active low output enable pins (/OE1 and /OE2) control all eight channels, and are configured so that both must be low for the outputs to be active.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
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* Data sheet SN74LV8T541-Q1 Automotive Octal Buffers and Drivers with 3-State Outputs and Logic-Level Shifter datasheet (Rev. A) PDF | HTML 09 Sep 2025

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 20 Ultra Librarian
VQFN (RKS) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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