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SN74LVC165A-Q1

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Automotive, 1.1V to 3.6V parallel-load eight-bit shift registers

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Data sheet

SN74LVC165A-Q1

ACTIVE
Data sheet Order now

Product details

Technology family LVC Input type CMOS Output type Push-Pull IOL (max) (mA) 24 IOH (max) (mA) -24 Features Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Automotive
Technology family LVC Input type CMOS Output type Push-Pull IOL (max) (mA) 24 IOH (max) (mA) -24 Features Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Automotive
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) WQFN (BQB) 16 8.75 mm² (3.5 mm × 2.5 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm)
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)

  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 20ns at 3.3V
  • Latch-up performance exceeds 100mAper JESD78 and AEC-Q100-004
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)

  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 20ns at 3.3V
  • Latch-up performance exceeds 100mAper JESD78 and AEC-Q100-004

The SN74LVC165A-Q1 contains one 8-bit parallel-load shift register. Data is loaded asynchronously using the shift or load (SH/LD) select pin. The device includes a serial (SER) input to allow for daisy chaining, and a standard (QH) and inverted (QH) output.

The SN74LVC165A-Q1 contains one 8-bit parallel-load shift register. Data is loaded asynchronously using the shift or load (SH/LD) select pin. The device includes a serial (SER) input to allow for daisy chaining, and a standard (QH) and inverted (QH) output.
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* Data sheet SN74LVC165A-Q1 Automotive 8-Bit Parallel-Load Shift Registers datasheet PDF | HTML May 30, 2024

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14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
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