NEW

SN74LVC1G125B-EP

ACTIVE

Enhanced product single 1.65-V to 5.5-V buffer with 3-state outputs

SN74LVC1G125B-EP

ACTIVE

Product details

Technology family LVC Number of channels 1 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family LVC Number of channels 1 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm)
  • Operating range from 1.1V to 5.5V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Latch-up performance exceeds 100mAper JESD 78
  • Supports defense and aerospace applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability
  • Operating range from 1.1V to 5.5V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Latch-up performance exceeds 100mAper JESD 78
  • Supports defense and aerospace applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability

The SN74LVC1G125B-EP device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable ( OE) input is high. When OE is low, true data is passed from the A input to the Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC1G125B-EP device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable ( OE) input is high. When OE is low, true data is passed from the A input to the Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Download View video with transcript Video

Technical documentation

No results found. Please clear your search and try again.
View all 2
Top documentation Type Title Format options Date
* Data sheet SN74LVC1G125B-EP Octal Buffers With 3-Stet Outputs datasheet PDF | HTML Jun 29, 2026
* Radiation & reliability report SN74LVC1G125B-EP Enhanced Product Qualification and Reliability Report PDF | HTML Mar 6, 2026

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Supported products & hardware
In stock
Limit:
??asset.out-of-stock-ti_en_US??
Not available
Package Pins CAD symbols, footprints & 3D models
SOT-23 (DBV) 5 Ultra Librarian

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos