Home Logic & voltage translation Flip-flops, latches & registers D-type flip-flops
Home
Logic & voltage translation
Flip-flops, latches & registers
D-type flip-flops

SN74LVC1G175-EP

ACTIVE

Enhanced Product Single D-Type Flip-Flop With Asynchronous Clear

Order now
Data sheet

SN74LVC1G175-EP

ACTIVE
Data sheet Order now

Product details

Number of channels 1 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
Number of channels 1 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm)
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in Military (–55°C/125°C)
      Temperature Range(1)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

(1) Additional temperature ranges available - contact factory
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in Military (–55°C/125°C)
      Temperature Range(1)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

(1) Additional temperature ranges available - contact factory

This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
filter Find other D-type flip-flops
Download View video with transcript Video

Technical documentation

No results found. Please clear your search and try again.
View all 4
Top documentation Type Title Format options Date
* Data sheet SN74LVC1G175-EP datasheet (Rev. A) Dec 14, 2010
* Radiation & reliability report CLVC1G175MDCKREP Reliability Report Nov 30, 2011
* VID SN74LVC1G175-EP VID V6206633 Jun 21, 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Package Pins CAD symbols, footprints & 3D models
SOT-SC70 (DCK) 6 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos