SN74LVC2G38

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2-ch, 2-input, 1.65-V to 5.5-V NAND gates with open-drain outputs

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Data sheet

document-pdfAcrobat Dual 2-Input NAND Gate With Open-Drain Outputs datasheet (Rev. D)

SN74LVC2G38

ACTIVE

Data sheet

Order now

Product details

Technology family

LVC

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

0

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

0

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SSOP (DCT)

8

11.8 mm² (2.95 mm × 4 mm)

VSSOP (DCU)

8

6.2 mm² (2 mm × 3.1 mm)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live insertion, Partial-Power-Down Mode Operation and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live insertion, Partial-Power-Down Mode Operation and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The SN74LVC2G38 is designed for 1.65-V to 5.5-V V_CC operation.

This device is a dual two-input NAND buffer gate with open-drain outputs. It performs the Boolean function Y = A • B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LVC2G38 is designed for 1.65-V to 5.5-V V_CC operation.

This device is a dual two-input NAND buffer gate with open-drain outputs. It performs the Boolean function Y = A • B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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