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SN74LVC373A

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1.65-V to 3.6-V, Octal Transparent D-Type Latch With 3-State Outputs

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Data sheet

SN74LVC373A

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 8 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) VQFN (RGY) 20 15.75 mm² (4.5 mm × 3.5 mm) SOP (NS) 20 98.28 mm² (12.6 mm × 7.8 mm) TVSOP (DGV) 20 32 mm² (5 mm × 6.4 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm) PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm)
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 6.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation
    on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Live-Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • On Products Compliant to MIL-PRF-38535, All
    Parameters Are Tested Unless Otherwise Noted.
    On All Other Products, Production Processing
    Does Not Necessarily Include Testing of All
    Parameters.
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 6.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation
    on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Live-Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • On Products Compliant to MIL-PRF-38535, All
    Parameters Are Tested Unless Otherwise Noted.
    On All Other Products, Production Processing
    Does Not Necessarily Include Testing of All
    Parameters.

The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

For all available packages, see the orderable addendum at the end of the data sheet.

The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

For all available packages, see the orderable addendum at the end of the data sheet.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SNx4LVC373A Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. T) PDF | HTML Nov 21, 2013
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
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Simulation model

SN74LVC373A IBIS Model

SCEM213.ZIP (40 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
VQFN (RGY) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
PDIP (N) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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