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SN74LVC8T245-Q1

ACTIVE

Automotive 8-Bit Dl-Spply Bus Trans. with Voltage Translation and Three-State Outputs

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Data sheet

SN74LVC8T245-Q1

ACTIVE
Data sheet Order now

Product details

Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO, PCM, SPI, UART, JTAG, I2S Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 6.6 Technology family LVC Supply current (max) (mA) 0.025 Rating Automotive Operating temperature range (°C) -40 to 125
Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO, PCM, SPI, UART, JTAG, I2S Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 6.6 Technology family LVC Supply current (max) (mA) 0.025 Rating Automotive Operating temperature range (°C) -40 to 125
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • AEC-Q100 qualified for automotive applications
  • Fully configurable dual-rail design allows each port to operate over the full 1.65V to 5.5V power-supply range
  • Robust, glitch-free power supply sequencing
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • VCC isolation feature and VCC disconnect feature
    • if either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high- impedance state
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • Operating temperature from -40°C to 125°C
  • ESD protection exceeds JESD 22
    • 4000V Human-Body Model (A114-A)
    • 1000V Charged-Device Model (C101)
  • AEC-Q100 qualified for automotive applications
  • Fully configurable dual-rail design allows each port to operate over the full 1.65V to 5.5V power-supply range
  • Robust, glitch-free power supply sequencing
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • VCC isolation feature and VCC disconnect feature
    • if either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high- impedance state
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • Operating temperature from -40°C to 125°C
  • ESD protection exceeds JESD 22
    • 4000V Human-Body Model (A114-A)
    • 1000V Charged-Device Model (C101)

The SN74LVC8T245-Q1 is an eight bit non-inverting bus transceiver with configurable dual power supply rails that enables bidirectional voltage level translation. The SN74LVC8T245-Q1 is optimized to operate with VCCA and VCCB set at 1.65V to 5.5V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5.5V voltage nodes.

The SN74LVC8T245-Q1 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated.

The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then all outputs are in the high-impedance state. To put the device in the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

The SN74LVC8T245-Q1 is designed so that the control pins (DIR and OE) are supplied by VCCA.

The SN74LVC8T245-Q1 is an eight bit non-inverting bus transceiver with configurable dual power supply rails that enables bidirectional voltage level translation. The SN74LVC8T245-Q1 is optimized to operate with VCCA and VCCB set at 1.65V to 5.5V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5.5V voltage nodes.

The SN74LVC8T245-Q1 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated.

The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then all outputs are in the high-impedance state. To put the device in the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

The SN74LVC8T245-Q1 is designed so that the control pins (DIR and OE) are supplied by VCCA.
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* Data sheet SN74LVC8T245-Q1 Automotive 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. B) PDF | HTML 29 May 2026
Selection guide Logic Guide (Rev. AC) PDF | HTML 13 Nov 2025
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
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Design & development

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