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SN74LVCC3245A

ACTIVE

Octal Bus Transceiver With Adjustable Output Voltage and 3-State Outputs

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Data sheet

SN74LVCC3245A

ACTIVE
Data sheet Order now

Product details

Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 2.3 Vin (max) (V) 3.6 Vout (min) (V) 3 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable Prop delay (ns) 11.2 Technology family LVC Supply current (max) (mA) 0.13 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 2.3 Vin (max) (V) 3.6 Vout (min) (V) 3 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable Prop delay (ns) 11.2 Technology family LVC Supply current (max) (mA) 0.13 Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 SOP (NS) 24 117 mm² 15 x 7.8 SSOP (DB) 24 63.96 mm² 8.2 x 7.8 SSOP (DBQ) 24 51.9 mm² 8.65 x 6 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • 8-bit direction controlled translating bus transceiver
  • 2.3V to 3.6V on A port and 3V to 5.5V on B port
  • Robust, glitch-free power supply sequencing
  • VCC isolation and VCC Disconnect feature
    • If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
  • Control inputs VIH and VIL levels are referenced to VCCA voltage
  • High drive strength for heavier loads: 24mA drive at 3V supply
  • Latch-up performance exceeds 250mA per JESD 17
  • Operating temperature range from -40°C to 85°C
  • ESD protection exceeds JESD 22
    • 2000V Human Body Model (A114-A)
    • 1000V Charged-Device Model (C101)
  • 8-bit direction controlled translating bus transceiver
  • 2.3V to 3.6V on A port and 3V to 5.5V on B port
  • Robust, glitch-free power supply sequencing
  • VCC isolation and VCC Disconnect feature
    • If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
  • Control inputs VIH and VIL levels are referenced to VCCA voltage
  • High drive strength for heavier loads: 24mA drive at 3V supply
  • Latch-up performance exceeds 250mA per JESD 17
  • Operating temperature range from -40°C to 85°C
  • ESD protection exceeds JESD 22
    • 2000V Human Body Model (A114-A)
    • 1000V Charged-Device Model (C101)

The SN74LVCC3245A device is an 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track VCCB, which accepts voltages from 3V to 5.5V, and the A port is designed to track VCCA, which operates at 2.3V to 3.6V. This allows for translation from a 3.3V to a 5V system environment and vice versa, from a 2.5V to a 3.3V system environment and vice versa.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling the outputs.

The SN74LVCC3245A device is an 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track VCCB, which accepts voltages from 3V to 5.5V, and the A port is designed to track VCCA, which operates at 2.3V to 3.6V. This allows for translation from a 3.3V to a 5V system environment and vice versa, from a 2.5V to a 3.3V system environment and vice versa.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling the outputs.
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Technical documentation

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* Data sheet SN74LVCC3245A Octal Bus Transceiver With Adjustable Output Voltage and 3-State Outputs datasheet (Rev. R) PDF | HTML 29 May 2026
Selection guide Logic Guide (Rev. AC) PDF | HTML 13 Nov 2025
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

AVCLVCDIRCNTRL-EVM — Generic EVM for Direction-Controlled Bidirectional Translation Device Supporting AVC and LVC

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

User guide: PDF
Not available on TI.com
Simulation model

HSPICE Model of SN74LVCC3245A

SCEJ159.ZIP (50 KB) - HSpice Model
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Simulation model

SN74LVCC3245A IBIS Model

SCAM033.ZIP (56 KB) - IBIS Model
Download
Package Pins CAD symbols, footprints & 3D models
SOIC (DW) 24 Ultra Librarian
SOP (NS) 24 Ultra Librarian
SSOP (DB) 24 Ultra Librarian
SSOP (DBQ) 24 Ultra Librarian
TSSOP (PW) 24 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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