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High Efficiency Secondary Side Synchronous Buck PWM Controller

Product details

Topology Buck Control mode Voltage Features Error amplifier, Soft start, Synchronization pin
Topology Buck Control mode Voltage Features Error amplifier, Soft start, Synchronization pin
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4
  • On-Chip Predictive Gate Drive™ for High-Efficiency Synchronous Buck Operation
  • Dual ±3-A TrueDrive™ Outputs
  • 1-MHz High Frequency Operation with 70-ns Delay from SYNCIN to G1 Output
  • Leading Edge Modulation
  • Overcurrent Protection using a Parallel Average Current Mode Control Loop
  • 3 Modes to Support 2.7-V to 35-V Bias Operation
  • Reverse Current Protection for Output Stage
  • User Programmable Shutdown
  • ±1.0% Initial Tolerance Bandgap Reference
  • High Bandwidth Error Amplifiers
  • Thermally Enhanced HTSSOP 20-Pin PowerPAD™ Package
  • APPLICATIONS
    • Secondary-Side Post Regulation (SSPR) for Multiple Output Power Supplies
    • Cascaded Buck Converters
    • Post Processing Converters for Bus Converter and DC Transformer Architectures

Predictive Gate Drive, TrueDrive, and PowerPAD are a trademarks of Texas Instruments Incorporated.

  • On-Chip Predictive Gate Drive™ for High-Efficiency Synchronous Buck Operation
  • Dual ±3-A TrueDrive™ Outputs
  • 1-MHz High Frequency Operation with 70-ns Delay from SYNCIN to G1 Output
  • Leading Edge Modulation
  • Overcurrent Protection using a Parallel Average Current Mode Control Loop
  • 3 Modes to Support 2.7-V to 35-V Bias Operation
  • Reverse Current Protection for Output Stage
  • User Programmable Shutdown
  • ±1.0% Initial Tolerance Bandgap Reference
  • High Bandwidth Error Amplifiers
  • Thermally Enhanced HTSSOP 20-Pin PowerPAD™ Package
  • APPLICATIONS
    • Secondary-Side Post Regulation (SSPR) for Multiple Output Power Supplies
    • Cascaded Buck Converters
    • Post Processing Converters for Bus Converter and DC Transformer Architectures

Predictive Gate Drive, TrueDrive, and PowerPAD are a trademarks of Texas Instruments Incorporated.

The UCC2540 is a secondary-side synchronous buck PWM controller for high current and low output voltage applications. It can be used either as the local secondary-side controller for isolated dc-dc converters using two-stage cascaded topologies or as a secondary-side post regulator (SSPR) for multiple output power supplies.

The UCC2540 runs with the synchronization signal from either the primary side or the high duty cycle quasi-dc output of bus converters or dc transformers. For higher efficiency, it also incorporates the Predictive Gate Drive™ technology that virtually eliminates body diode conduction losses in synchronous rectifiers.

The UCC2540 is available in the extended temperature range of –40°C to 105°C and is offered in thermally enhanced PowerPAD™ 20-pin HTSSOP (PWP) package. This space saving package with standard 20-pin TSSOP footprint has a drastically lower thermal resistance of 1.4°C/W øJC to accommodate the dual high-current drivers on board.

The UCC2540 is a secondary-side synchronous buck PWM controller for high current and low output voltage applications. It can be used either as the local secondary-side controller for isolated dc-dc converters using two-stage cascaded topologies or as a secondary-side post regulator (SSPR) for multiple output power supplies.

The UCC2540 runs with the synchronization signal from either the primary side or the high duty cycle quasi-dc output of bus converters or dc transformers. For higher efficiency, it also incorporates the Predictive Gate Drive™ technology that virtually eliminates body diode conduction losses in synchronous rectifiers.

The UCC2540 is available in the extended temperature range of –40°C to 105°C and is offered in thermally enhanced PowerPAD™ 20-pin HTSSOP (PWP) package. This space saving package with standard 20-pin TSSOP footprint has a drastically lower thermal resistance of 1.4°C/W øJC to accommodate the dual high-current drivers on board.

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* Data sheet High-Efficiency Secondary Side Synchronous PWM Controller datasheet (Rev. C) 10 Oct 2008

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