CD74ACT175

ACTIVE

Quad D-Type Flip-Flops with Reset

Product details

Number of channels 4 Technology family ACT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 114 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 80 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 4 Technology family ACT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 114 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 80 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm)
  • Inputs are TTL-voltage compatible
  • Contains four flip-flops with double-rail outputs
  • Buffered inputs
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Balanced propagation delays
  • ±24mA output drive current
    • Fanout to 15 F devices
  • SCR-latchup-resistant CMOS process and circuit design
  • Inputs are TTL-voltage compatible
  • Contains four flip-flops with double-rail outputs
  • Buffered inputs
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Balanced propagation delays
  • ±24mA output drive current
    • Fanout to 15 F devices
  • SCR-latchup-resistant CMOS process and circuit design

This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features complementary outputs from each flip-flop.

This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features complementary outputs from each flip-flop.

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CD74AC175 ACTIVE Quad D-Type Flip-Flops with Reset Voltage range 2V to 6V, average propagation delay 7ns, average drive strength 24mA

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet CD74ACT175 Quadruple D-type Flip-Flop with Clear datasheet (Rev. A) PDF | HTML May 8, 2024
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian

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