Información de empaque
| Encapsulado | Pines VQFN (RGZ) | 48 |
| Rango de temperatura de funcionamiento (℃) -40 to 85 |
| Cant. de paquetes | Transportador 250 | SMALL T&R |
Características para ADS41B25
- Resolution: 12-Bit, 125MSPS
- Integrated High-Impedance
Analog Input Buffer:- Input Capacitance at dc: 3.5pF
- Input Resistance at dc: 10kΩ
- Maximum Sample Rate: 125MSPS
- Ultralow Power:
- 1.8V Analog Power: 114mW
- 3.3V Buffer Power: 96mW
- I/O Power: 100mW (DDR LVDS)
- High Dynamic Performance:
- SNR: 68.3dBFS at 170MHz
- SFDR: 87dBc at 170MHz
- Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
- Standard Swing: 350mV
- Low Swing: 200mV
- Default Strength: 100Ω Termination
- 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
- Programmable Gain for SNR/SFDR Trade-Off
- DC Offset Correction
- Supports Low Input Clock Amplitude
- Package: QFN-48 (7mm × 7mm)
PowerPAD is a trademark of Texas Instruments, Incorporated.
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Descripción de ADS41B25
The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with the benefits of constant performance and input impedance across a wide frequency range. The device is well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.
The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
The device supports both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500MBPS) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The device has a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.
The device is available in a compact QFN-48 package and is specified over the industrial temperature range (–40°C to +85°C).