Información de empaque
| Encapsulado | Pines WQFN (RTA) | 40 |
| Rango de temperatura de funcionamiento (℃) -40 to 105 |
| Cant. de paquetes | Transportador 2,500 | LARGE T&R |
Características para DS90UB903Q-Q1
- 10 MHz to 43 MHz Input PCLK Support
- 210 Mbps to 903 Mbps Data Throughput
- Single Differential Pair Interconnect
- Bidirectional Control Interface Channel with I2C Support
- Embedded Clock with DC Balanced Coding to Support AC-Coupled Interconnects
- Capable to Drive up to 10 Meters Shielded Twisted-Pair
- I2C Compatible Serial Interface
- Single Hardware Device Addressing Pin
- Up to 4 General Purpose Input (GPI)/ Output (GPO)
- LOCK Output Reporting Pin and AT-SPEED BIST Diagnosis Feature to Validate Link Integrity
- Integrated Termination Resistors
- 1.8V- or 3.3V-Compatible Parallel Bus Interface
- Single Power Supply at 1.8V
- ISO 10605 ESD and IEC 61000-4-2 ESD Compliant
- Automotive Grade Product: AEC-Q100 Grade 2 Qualified
- Temperature Range −40°C to +105°C
- No Reference Clock Required on Deserializer
- Programmable Receive Equalization
- EMI/EMC Mitigation
- DES Programmable Spread Spectrum (SSCG) Outputs
- DES Receiver Staggered Outputs
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Descripción de DS90UB903Q-Q1
The DS90UB903Q/DS90UB904Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB903Q/904Q incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with bidirectional control channel bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.