Información de empaque
| Encapsulado | Pines QFM (SIA) | 8 |
| Rango de temperatura de funcionamiento (℃) -40 to 85 |
| Cant. de paquetes | Transportador 2,500 | LARGE T&R |
Características para LMK61E2
- Ultra-Low Noise, High Performance
- Jitter: 90 fs RMS Typical fOUT > 100 MHz
- PSRR: –70 dBc, Robust Supply Noise Immunity
- Flexible Output Format; User Selectable
- LVPECL up to 1 GHz
- LVDS up to 900 MHz
- HCSL up to 400 MHz
- Total Frequency Tolerance of ±50 ppm
- System Level Features
- Frequency Margining: Fine and Coarse
- Internal EEPROM: User Configurable Default Settings
- Other Features
- Device Control: I2C
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7-mm × 5-mm 8-Pin Package
- Create a Custom Design Using the LMK61E2 With the WEBENCH® Power Designer
Descripción de LMK61E2
The LMK61E2 device is an ultra-low jitter PLLatinum programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that generates commonly used reference clocks. The outputs can be configured as LVPECL, LVDS, or HCSL.
The device features self start-up from on-chip EEPROM that is factory programmed to generate 156.25-MHz LVPECL output. The device registers and EEPROM settings are fully programmable in-system through I2C serial interface. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ± 5% supply.
The device provides fine and coarse frequency margining options through I2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin testing.