Información de empaque
| Encapsulado | Pines TSSOP (PW) | 20 |
| Rango de temperatura de funcionamiento (℃) -40 to 125 |
| Cant. de paquetes | Transportador 70 | TUBE |
Características para SN74LV240A
- VCC operation of 2 V to 5.5 V
- Max tpd of 6.5 ns at 5 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
- Support Mixed-Mode Voltage Operation on All Ports
- Latch-Up Performance Exceeds 250 mA per JESD 17
- Ioff Supports Live Insertion, Partial Power-Down Mode, and Back Drive Protection
Descripción de SN74LV240A
These octal buffers/drivers with inverted outputs are designed for 2 V to 5.5 V VCC operation.
The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.