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SN74LV11A

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3-ch, 3-input 2-V to 5.5-V high-speed (7 ns) AND gate

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Data sheet

SN74LV11A

ACTIVE
Data sheet Order now

Product details

Technology family LV-A Number of channels 3 Inputs per channel 3 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LV-A Number of channels 3 Inputs per channel 3 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm) TVSOP (DGV) 14 23.04 mm² (3.6 mm × 6.4 mm)
  • Operation of 2V to 5.5V VCC
  • Max tpd of 7ns at 5V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • Operation of 2V to 5.5V VCC
  • Max tpd of 7ns at 5V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II

These triple 3-input positive-AND gates are designed for 2V to 5.5V VCC operation.

These triple 3-input positive-AND gates are designed for 2V to 5.5V VCC operation.
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Technical documentation

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* Data sheet SN74LV11A Triple 3-Input Positive-AND Gates datasheet (Rev. E) PDF | HTML May 23, 2024

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Supported products & hardware
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Simulation model

SN74LV11A Behavioral SPICE Model

SCEM658.ZIP (8 KB) - PSpice model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SSOP (DB) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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