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SN74LVC10A

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Three-channel, three-input, 1.65V to 3.6V NAND gates

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Data sheet

SN74LVC10A

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 3 Inputs per channel 3 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 3 Inputs per channel 3 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
VQFN (RGY) 14 12.25 mm² (3.5 mm × 3.5 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm)
  • Operates from 1.65V to 3.6V
  • Specified from –40°C to 85°C and –40°C to 125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.9ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250 mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
  • Operates from 1.65V to 3.6V
  • Specified from –40°C to 85°C and –40°C to 125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.9ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250 mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)

This triple 3-input positive-NAND gate is designed for 1.65V to 3.6V VCC operation.

This triple 3-input positive-NAND gate is designed for 1.65V to 3.6V VCC operation.
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Technical documentation

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* Data sheet SN74LVC10A Triple 3-Input Positive-NAND Gate datasheet (Rev. Q) PDF | HTML Aug 2, 2024

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
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Simulation model

SN74LVC10A Behavioral SPICE Model

SCAM112.ZIP (8 KB) - PSpice model
Supported products & hardware
Simulation model

SN74LVC10A IBIS Model (Rev. A)

SCEM011 (8 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
VQFN (RGY) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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