封裝資訊
| 封裝 | 引腳 FCCSP (AAV) | 144 |
| 作業溫度範圍 (°C) -40 to 85 |
| 包裝數量 | 運送包裝 168 | JEDEC TRAY (5+1) |
ADC12DJ2700 的特色
- ADC core:
- 12-bit resolution
- Up to 5.4 GSPS in single-channel mode
- Up to 2.7 GSPS in dual-channel mode
- Performance
specifications:
- Noise floor (no signal, VFS = 1.0
VPP-DIFF):
- Dual-channel mode: –151.6 dBFS/Hz
- Single-channel mode: –153.8 dBFS/Hz
- HD2, HD3: –65 dBc up to 3 GHz
- Noise floor (no signal, VFS = 1.0
VPP-DIFF):
- Buffered analog inputs
with VCMI of 0 V:
- Analog input bandwidth (–3 dB): 8.0 GHz
- Usable input frequency range: >10 GHz
- Full-scale input voltage (VFS, default): 0.8 VPP
- Analog input common-mode (VICM): 0 V
- Noiseless aperture delay (TAD)
adjustment:
- Precise sampling control: 19-fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204B serial data interface:
- Supports subclass 0 and 1
- Maximum lane rate: 12.8 Gbps
- Up to 16 lanes allows reduced lane rate
- Digital down-converters in dual-channel
mode:
- Real output: DDC bypass or 2x decimation
- Complex output: 4x, 8x, or 16x decimation
- Four independent 32-Bit NCOs per DDC
- Power consumption: 2.7 W
- Power supplies: 1.1 V, 1.9 V
ADC12DJ2700 的說明
The ADC12DJ2700 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ2700 can sample up to 2700 MSPS and up to 5400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ2700 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).