封裝資訊
| 封裝 | 引腳 NFBGA (ZAY) | 196 |
| 作業溫度範圍 (°C) -40 to 85 |
| 包裝數量 | 運送包裝 160 | JEDEC TRAY (5+1) |
ADS54T01 的特色
- Single channel
- 12-bit resolution
- Maximum clock rate: 750 Msps
- Low swing fullscale input: 1.0 Vpp
- Analog input buffer with high impedance input
- Input bandwidth (3 dB): > 1.2 GHz
- Data output interface: DDR LVDS
- 196-Pin NFBGA package (12 mm × 12 mm)
- Power dissipation: 1.2 W
- Performance at fin = 230 MHz IF
- SNR: 60.7 dBFS
- SFDR: 73 dBc
- Performance at fin = 700 MHz IF
- SNR: 58.6 dBFS
- SFDR: 64 dBc
- Receive mode: 2x decimation with low-pass or high-pass filter
- Feedback mode: burst mode output for full bandwidth DPD feedback
ADS54T01 的說明
The ADS54T01 is a high linearity, single channel, 12-bit, 750-Msps analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input.
Two output modes are available for the output data—the data can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high-resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196-pin NFBGA package and is specified over the full industrial temperature range (–40°C to 85°C).