封裝資訊
| 封裝 | 引腳 VQFN (RGZ) | 48 |
| 作業溫度範圍 (°C) -40 to 125 |
| 包裝數量 | 運送包裝 2,000 | LARGE T&R |
DP83869HM 的特色
- Multiple operating modes
- Media support: copper and fiber
- Media conversion between copper and fiber
- Bridge between RGMII and SGMII
- Maximum ambient temperature available of 125°C
- Exceeds 8kV IEC61000-4-2 ESD
- Low power consumption
- < 150mW for 1000Base-X
- < 500mW for 1000Base-T
- Low RGMII latency
- Total latency ≤ 384ns for 1000Base-T
- Total latency ≤ 361ns for 100Base-TX
- Time Sensitive Network (TSN) compliant
- Recovered clock output for SyncE
- Selectable synchronized clock output: 25MHz and 125MHz
- SFF-8431 V4.1, 1000BASE-X and 100BASE-FX Compatible
- IEEE1588 support via SFD
- Wake on LAN support
- Configurable IO voltages: 1.8V, 2.5V, and 3.3V
- SGMII, RGMII, MII MAC interface
- Jumbo frame support for 1000M and 100M speed
- Cable diagnostics
- TDR
- BIST
- Programmable RGMII termination impedance
- Integrated MDI termination resistor
- Fast link drop modes
- Conforms to IEEE 802.3 1000Base-T, 100Base-TX, 10Base-Te,1000Base-X, 100Base-FX
DP83869HM 的說明
The DP83869HM device is a robust, fully-featured gigabit physical layer (PHY) transceiver with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and 100BASE-FX fiber protocols. Optimized for ESD protection, the DP83869HM exceeds 8kV IEC 61000-4-2 (direct contact).This device interfaces to the MAC layer through reduced GMII (RGMII) and SGMII. In 100M mode, the device lets the designer use MII for lower latency. Programmable integrated termination impedance on RGMII/MII helps reduce system BOM.
The DP83869HM supports media conversion in unmanaged mode. In this mode, the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX conversions.
The DP83869HM can also support bridge conversion from RGMII to SGMII and SGMII to RGMII. The DP83869HM is compliant to TSN standards and offers low latency.
The DP83869HM can also generate IEEE 1588 Sync Frame Detect indications to MAC. This can reduce the jitter in Time Synchronization and help the System account for asymmetric delays in Transmission and Reception of packets.
The standard Ethernet system block diagram is shown on the first page. Designers can also use the DP83869 in Media Convertor mode, in RGMII-to-SGMII Bridge applications, and in SGMII-RGMII Bridge applications.