封裝資訊
| 封裝 | 引腳 WQFN (NJY) | 54 |
| 作業溫度範圍 (°C) -10 to 85 |
| 包裝數量 | 運送包裝 250 | SMALL T&R |
DS50PCI402 的特色
- Input and Output signal conditioning increases PCIe reach in backplanes and cables
- 0.09 UI of residual deterministic jitter at 5Gbps after 42” of FR4 (with Input EQ)
- 0.11 UI of residual deterministic jitter at 5Gbps after 7m of PCIe Cable (with Input EQ)
- 0.09 UI of residual deterministic jitter at 5Gbps with 28” of FR4 (with Output DE)
- 0.13 UI of residual deterministic jitter at 5Gbps with 7m of PCIe Cable (with Output DE)
- Adjustable Transmit VOD 800 to 1200mVp-p
- Automatic and manual Receiver Detection and input termination control circuitry
- Automatic power management on an individual lane basis via SMBus
- Adjustable electrical idle detect threshold.
- Data rate optimized 3-stage equalization to 27 dB gain
- Data rate optimized 6-level 0 to 12 dB transmit de-emphasis
- Flow-thru pinout in 10mmx5.5mm 54-pin leadless WQFN package
- Single supply operation at 2.5V
- >6kV HBM ESD rating
- -10 to 85°C operating temperature range
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DS50PCI402 的說明
The DS50PCI402 is a low power, 4 lane bidirectional buffer/equalizer designed specifically for PCI Express Gen1 and Gen2 applications. The device performs both receive equalization and transmit de-emphasis, allowing maximum flexibility of physical placement within a system. The receiver is capable of opening an input eye that is completely closed due to inter-symbol interference (ISI) induced by the interconnect medium.
The transmitter de-emphasis level can be set by the user depending on the distance from the DS50PCI402 to the PCI Express endpoint. The DS50PCI402 contains PCI Express specific functions such as Transmit Idle, RX Detection, and Beacon signal pass through.
The device provides automatic receive detection circuitry which controls the input termination impedance. By automatically reflecting the current load impedance seen on the outputs back to the corresponding inputs the DS50PCI402 becomes completely transparent to both the PCIe root complex and endpoint. An internal rate detection circuit is included to detect if an incoming data stream is at Gen2 data rates, and adjusts the de-emphasis on it's output accordingly. The signal conditioning provided by the device allows systems to upgrade from Gen1 data rates to Gen2 without reducing their physical reach. This is true for FR4 applications such as backplanes, as well as cable interconnect.