OMAP5910JZVL2 現行

• Low-Power, High-Performance CMOS Technology
  • 0.13-µm Technology
  • 1.6-V Core Voltage
• TI925T (MPU) ARM9TDMI™ Core
  • Support 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
  • 16K-Byte Instruction Cache
  • 8K-Byte Data Cache
  • Data and Program Memory Management Units (MMUs)
  • Two 64-Entry Translation Look-Aside Buffers (TLBs) for MMUs
  • 17-Word Write Buffer
• TMS320C55x™ (C55x™) DSP Core
  • One/Two Instructions Executed per Cycle
  • Dual Multipliers (Two Multiply-Accumulates per Cycle)
  • Two Arithmetic/Logic Units
  • One Internal Program Bus
  • Five Internal Data/Operand Buses (3 Read Buses and 2 Write Buses)
  • 32K x 16-Bit On-Chip Dual-Access RAM (DARAM) (64K Bytes)
  • 48K x 16-Bit On-Chip Single-Access RAM (SARAM) (96K Bytes)
  • 16K x 16-Bit On-Chip ROM (32K Bytes)
  • Instruction Cache (24K Bytes)
  • Video Hardware Accelerators for DCT, IDCT, Pixel Interpolation, and Motion Estimation for Video Compression
• 192K Bytes of Shared Internal SRAM
• Memory Traffic Controller (TC)
  • 16-Bit EMIFS External Memory Interface to Access up to 128M Bytes of Flash, ROM, or ASRAM
  • 16-Bit EMIFF External Memory Interface to Access up to 64M Bytes of SDRAM
• 9-Channel System DMA Controller
• DSP Memory Management Unit
• Endianism Conversion Logic
• Digital Phase-Locked Loop (DPLL) for MPU/DSP/TC Clocking Control
• DSP Peripherals
  • Three 32-Bit Timers and Watchdog Timer
  • Level1/Level2 Interrupt Handlers
  • Six-Channel DMA Controller
  • Two Multichannel Buffered Serial Ports
  • Two Multichannel Serial Interfaces
• TI925T Peripherals
  • Three 32-Bit Timers and Watchdog Timer
  • 32-kHz Timer
  • Level1/Level2 Interrupt Handlers
  • USB (Full/Low Speed) Host Interface With up to 3 Ports
  • USB (Full Speed) Function Interface
  • One Integrated USB Transceiver for Either Host or Function
  • Multichannel Buffered Serial Port
  • Inter-Integrated Circuit (I²C) Master and Slave Interface
  • Microwire™ Serial Interface
  • Multimedia Card (MMC) and Secure Digital (SD) Interface
  • HDQ/1-Wire® Interface
  • Camera Interface for CMOS Sensors
  • ETM9 Trace Module for TI925T Debug
  • Keyboard Matrix Interface (6 x 5 or 8 x 8)
  • Up to Ten MPU General-Purpose I/Os
  • Pulse-Width Tone (PWT) Interface
  • Pulse-Width Light (PWL) Interface
  • Two LED Pulse Generators (LPGs)
  • Real-Time Clock (RTC)
  • LCD Controller With Dedicated System DMA Channel
• Shared Peripherals
  • Three Universal Asynchronous Receiver/Transmitters (UARTs) (One Supporting SIR Mode for IrDA)
  • Four Interprocessor Mailboxes
  • Up to 14 Shared General-Purpose I/Os
• Individual Power-Saving Modes for MPU/DSP/TC
• On-Chip Scan-Based Emulation Logic
• IEEE Std 1149.1 (JTAG) Boundary Scan Logic
• Two 289-Ball MicroStar BGA™ (Ball Grid Array) Package Options (GZG and GDY Suffixes)

TMS320C55x, C55x, and MicroStar BGA are trademarks of Texas Instruments.
ARM9TDMI is a trademark of ARM Limited.
Thumb is a registered trademark of ARM Limited.
Microwire is a trademark of National Semiconductor Corporation.
1-Wire is a registered trademark of Dallas Semiconductor Corporation.
IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
OMAP and DSP/BIOS are trademarks of Texas Instruments.
Bluetooth is a trademark owned by Bluetooth SIG, Inc.
Windows is a registered trademark of Microsoft Corporation.
Other trademarks are the property of their respective owners.