封裝資訊
封裝 | 引腳 PDIP (N) | 14 |
作業溫度範圍 (°C) -40 to 85 |
包裝數量 | 運送包裝 25 | TUBE |
SN74ACT74 的特色
- 4.5-V to 5.5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 10.5 ns at 5 V
- Inputs Are TTL-Voltage Compatible
SN74ACT74 的說明
The ACT74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.