Pricing, Availability and Roadmap
Q. What is available today for the C55x and the C64x?
A. eXpressDSP development tools, on-line training and technical documentation for each of the cores are available today. Check out www.ti.com/sc/twonewdsps for more information.
Q. When will the first C64x devices be available?
A. The first product announcement is scheduled for later in 2000. eXpressDSP development tools, technical documentation and training are available now so customers can start developing today. Because the C64x devices are fully object code compatible with the C62x, customers can use C62x silicon today and then easily move to the C64x when needed for increased performance, knowing that their software investment is fully protected.
Q. When can we expect to see 1.1GHz devices from TI?
A. The first C64x devices will have speeds ranging from 600-800MHz this year. A 1.1GHz device is expected in 2001.
Q. When will the first C55x devices be available?
A. We are already sampling silicon to key wireless OEMs, including Nokia for next generation 3G cell phones. The first product announcement is scheduled for Spring 2000. eXpressDSP development tools, technical documentation and training are available now so customers can start developing today.
Q. What configurations of C64x and C55x devices will you be shipping this year?
A. Details will be available when the devices are announced later this year. You can rest assured that the performance of the memory and peripherals will be appropriate for the levels of CPU performance offered on these new cores. To give you an idea of how these cores are expected to proliferate over time, we have 8 different C62x/C67x devices and 14 different configurations for the C54x. You can expect to see similar product line breadth with the C64x and the C55x over time.
Q. Will there be pin compatible versions of the C55x with existing C54x devices? What about pin compatible versions of the C64x with existing C62x devices?
A. If the peripheral sets of the new devices are identical to those of an existing device, then the goal is pin compatibility between them. However, some scaling of the C54x and C62x peripherals is likely to keep up with the performance of the new C55x and C64x cores. Thus, pin compatibility with existing devices cannot be assured for all future C55x and C64x devices.
Q. What is the price for the initial C64x and C55x devices?
A. Prices for the initial devices will be available when they are announced. Over time, we expect to have offer a wide range of price/performance points for both product lines.
Q. How will TI's announcement of the new cores impact the C54x and C62x/C67x product lines?
A. TI's current C5000 and C6000 generations will continue to thrive and grow. The C55x and C64x cores give our customers a software compatible roadmap to the next level of DSP technology leadership and an even wider selection to pick and choose from in our DSP catalog.
Q. Will the VelociTI.2 enhancements support floating point DSP? If yes, will they have multiprocessing capability?
A. While the first C64x devices will be fixed point, TI plans to support floating point with the VelociTI.2 enhancements in the future. Similar to the C62x and C67x, customers can expect code compatibility between the fixed and floating point implementations. TI is currently evaluating various types of multiprocessing solutions.
Q. When will mil-spec versions of the C55x and the C64x become available?
A. TI's military semiconductor products group will release details on possible mil-spec versions after the first commercial devices have been announced.
Q. Are there plans for multi-core versions of the C55x and C64x?
A. TI has been using proven silicon on a chip technology (SOC) to build multi-core DSPs on a single die for sometime. Our C5420, C5421 and recently announced C5441 demonstrate our long-term commitment to that strategy. Multi-core C55x and C64x devices are possible in the future.
Q. Does TI have plans for RAMBUS support on the C55x or the C64x?
A. TI is evaluating RAMBUS support for future devices.
Q. Does TI have plans for integrating ADC/DAC capabilities on the C55x?
A. TI's DSP and analog teams work closely together on future roadmaps. The integration of data converter functions with DSPs has been done for key vertical customers and is under evaluation for future catalog products.
Q. Will TI ever integrate and FPGA or PLD on-chip with the C55x or C64x?
A. Numerous types of peripherals are under consideration for future C5000 and C6000 derivatives.
Q. When will there be tools available for each?
A. For both C55x and C64x, initial tools are available now to qualified customers. Full production tools supporting the C55x and C64x are scheduled for availability in April 2000 when a new release of Code Composer Studio becomes available. Registered users of Code Composer Studio for the C5000 and/or the C6000 will begin receiving the new release in April.
Q. What is the price of the tools for the C55x and the C64x?
A. New customers will need to purchase Code Composer Studio for the C5000 and/or the C6000. Code Composer Studio sells for $2995. 30-day free evaluation tools are also expected to become available on the TI web site in April.
Q. Will TI offer evaluation modules and low cost DSP starter kits for the C55x and the C64x?
A. Evaluation modules for both the C55x and the C64x are expected to be available later this year. DSP starter kits are also planned for future derivatives.
Q. What are TI's plans for supporting C++, Java, and Linux on the C55x and/or C64x?
A. TI's newest version of Code Composer Studio supports C++. TI is a licensee of Java and is evaluating various support options. TI is also evaluating Linux support options.
Q. What are TI's plans for supporting real-time operating systems for these two new cores?
A. Both the C55x and the C64x will be supported by the new release of Code Composer Studio that will begin shipping to customers in April. Code Composer Studio includes TI's DSP BIOS, a scalable, real-time foundation kernel which speeds the time-to-market of advanced signal processing systems. Other third parties RTOS vendors are also planning to offer support for the new cores as part of TI's eXpress DSP software initiative.
Q. What are TI's plans for emulation support for the new architectures?
A. TI's existing XDS510 emulators will support the new cores. Enhancements to the existing emulators are also under development to more fully exploit the advanced emulation features of the new cores.
Q. Will TI ever offer "push button" programming for DSPs with high-level function integration?
A. TI's third party network features companies offering high-level function support. Key companies working in this area include Hyperception and the MathWorks. Check out TI's
Q. What is the time-to-market savings with these new cores?
A. TI's eXpress DSP software inititative, which fully supports the new cores, offers reductions of 50% and more on typical DSP applications..
Q. What are TI's plans for university support of the new cores?
A. TI works closely with leading universities around the world. Universities who are interested in working on projects with the new cores should contact TI's University Relations Team at http://www.ti.com/sc/university for more information.
Q. Why do I need a DSP instead of a general purpose microprocessor?
A. DSPs perform different types of work than traditional microprocessors. Digital Signal Processors are very high performance processors that enable electronic equipment to perform functions in real time. Communications equipment, such as DSL modems and wireless handsets, requires instantaneous response. Traditional microprocessor architectures do not provide the same levels of real-time performance. Moreover, the power dissipation for general purpose microprocessor architectures continues to be higher than that of the most power efficient DSPs.
Q. What is the significance of programmable DSPs?
A. Programmable DSPs reduce costs to the end user and speed time to market. They are flexible and adaptable to the fast pace of product innovation. Product features can be implemented in software and can often be enhanced with an after-market software upgrade. This is especially important for products tied to evolving standards.
Q. Why should I care about DSP software compatibility?
A. The DSP market continues to diversify and grow. Product developers need to focus on innovations rather than rewriting DSP code. TI's customers can reuse their software and leverage software from our many 3rd parties.
Return to top
Applications
Broadband (DSL and Cable)
Q. What are TI's DSL chipset plans for the use of the new DSPs?
A. TI will integrate the C64x DSP core technology into high-speed, low-power DSL chipsets that will allow for a binder group on a chip enabling up to 32 lines on a single transceiver chip for central office applications. TI will also use the new C64x to enable higher-bit rates and extend the DSL roadmap to include next generation DSL advancements and services.
Q. Does this new DSP core technology give TI any advantages over competitive DSL chipset vendors?
A. The increased MIPS and low power consumption of the new C64x DSP core technology will accelerate TI's central office (CO) roadmap in port density and reduced power chipsets. C64x enabled chipsets will allow TI to maintain measurable distances from its competitors in offerings for digital subscriber line access multiplexers (DSLAMs), digital loop carriers (DLCs) and CO line cards in the upcoming years.
Q. When will TI introduce DSL chipsets based on this new DSP core?
A. TI expects to have DSL chipsets based on the C64x DSP core in mid 2001.
Q. Will the C64x DSP core be used in CO or CPE applications?
A. The additional MIPS and low-power consumption of the C64x DSP core technology make it an ideal solution for central office applications where the additional MIPS will allow for eight times the amount of ports with reduced power consumption than chipsets currently available on the market. For CPE applications, with the addition of the C64x core, TI is positioned to meet higher ADSL speeds and accommodate additional services that CPE chipsets may require in the future.
Q. Will new products based on this DSP core be compatible with the current 'C62x cores currently being used in TI's DSL chipsets?
A. One of the benefits of TI DSP-enabled DSL chipsets is that each generation is code-compatible with previous generations. This enables current customers to migrate to the next generation of chipsets without worrying about encountering incompatibility issues with the current chipsets that they use.
Q. What advantage does full programmability offer DSL customers? Why is this important?
A. Full programmability means complete investment protection for our customers because they can confidently deploy future-proofed solutions and meet the market's demand for high-speed Internet access today. This programmability also ensures quick time to market because changes can be made via software, not complicated ASIC re-designs. Modems based on TI's fully programmable DSPs also can be easily upgraded via software downloads as technology evolves. Also important to DSL modem manufacturers, TI's single chipset can support all the essential standards for delivering ADSL today-T1.413 issue 2, ITU G.992.2 and G.992.1 and v.90, the analog modem standard. Looking ahead, solutions based on TI's fully programmable DSPs allow for differentiation because designers can easily add new features such as security, VPNs, voice and more.
Q. Which of the two new cores will be used for TI cable modem products?
A. TI's current voice-enabled cable modem products are based on the TMS320C54x. Thus, TI's code compatible C55x is planned for TI's future cable modem client premise equipment (CPE) systems. It has the potential to cut power consumption in half within the DSP subsystem of the cable modem. Low power consumption is critical to power-sensitive cable modem applications, such as the Broadband Telephony Interface (BTI), since OEMs must keep their systems operating within the limited power budget of network-powered cable modem installations. The energy saving C55x also offers five times the performance of comparable low-power DSPs today which will give cable modem CPE equipment the performance to fuel next-generation applications like wideband vocoders, streaming audio and video conferencing. The C64x is likely to increase in importance in cable modem products as video content proliferates and as the cable modem morphs into a residential gateway.
Q. When can we expect to see C55x devices in TI's cable modem products?
A. TI expects to begin integration this year with initial shipments expected in 2001.
Q. Does this new DSP core technology give TI any advantages over competitive cable modem vendors?
A. Yes. No other cable modem vendor today is shipping programmable DSP products as part of their cable modem portfolio. TI's new cores extend this leadership with significantly higher performance, but more importantly, TI brings more than just cores to the game. TI offers a comprehensive portfolio of cores, devices, software products, development tools, and third parties which combine to make differentiation far more accessible to our customers.
Q. Will new products based on the cores be compatible with the current DSP cores currently being used in TI's cable modem products?
A. Absolutely. This is a major customer benefit to preserve their system investment. Ultimately, software compatible platforms enable faster time-to-market as well by giving OEMs a future-proof platform in which new product development does not require starting over from scratch on system software. It also means that hundreds of third parties with C54x and C62x software can immediately provide software products to TI's next-generation C55x and C64x customers.
Return to top
Wireless
Q. How will these DSP cores impact TI's wireless market position going into 3G?
A. For 3G you'll have TI DSPs on both sides of the connection. TI's C55x will serve as the engine for 3G wireless handsets and our C64x will power wireless infrastructure such as 3G basestations. Nokia and Ericsson have already selected the C55x for 3G handsets. Both have also announced their plans to use our Open Mulitimedia Application Platform (OMAP), again C55x based, for their implementations across all next-generation standards, starting with 2.5G and continuing into 3G. Although handsets get most of the attention, we have engagements with 8 of the world's top 10 basestation manufacturers for C6000 based solutions.
Q. What is OMAP?
A. Open Mulitimedia Application Platform (OMAP) combines the C55x DSP and software interfaces or APIs that will enable 3rd parties to write multimedia applications accelerated by the DSP for wireless Smartphones, PDAs and other digital internet appliances.
Q. How will these cores compare with competitor offerings for 3G wireless applications?
- We believe TI's C55x and C64x offers wireless OEMs the best solution for their 3G requirements.
- For advanced, 3G wireless handsets and mobile computing devices, the TMS320C55x delivers ultra-low power consumption of 0.05 milliWatts per Million Instructions per Second (MIPS), six times lower than the industry leading C54x and any competitor in this space. As a result, the 'C55x will extend battery life in 3G handsets, allowing wireless end users to take advantage of advanced functionality and data services, without surrendering wireless convenience and portability.
- For next-generation phones, TI is already publicly engaged with two of the world's leading phone manufacturers: Nokia and Ericsson. These two companies, combined, represent nearly half of today's digital cell-phone production.
- Both announced their plans to use TI's C55x enabled Open Multimedia Application Platform (OMAP) for their implementations across all next-generation standards, starting with 2.5G and continuing into 3G.
- TI's next generation TMS320C64x DSP core is ideal for the needs of wireless infrastructure manufacturers, delivering the highest performance DSPs in the world, with scalable speeds of up to 1.1 GigaHertz (GHz) and performance near 9,000 MIPS.
- In 3G basestations, TI has significantly increased its market position from 2G, having engagements now with 8 of the world's top 10 base station manufacturers. The C64x platform will help to extend TI's leadership in wireless infrastructures.
- Both cores also have the benefit of code and pin-for-pin compatibility with the C54x and C64x DSPs.
Return to top
Imaging/Video
Q. How will the new C64x DSP core impact TI's market position in imaging?
A. The C64x will drive both performance and quality of imaging applications to unprecedented levels, which will increase the use of color printers, copiers and scanners in office and home environments. For instance, if the C64x replaced a RISC processor in one of today's 4 - 6 ppm color laser printers, you would see an increase in color printer performance to 36 ppm. Consumers could print color photos from an entire roll of film in seconds vs. minutes.
Q. What are the benefits of the C64x to printer, scanner and copier OEMs?
A. When OEMs replace ASIC or RISC-based solutions with a fully programmable C64x DSP core from TI, they will achieve better performance and lower cost with faster time to market. The C64x DSP brings the benefits of scalability across the OEMs complete range of imaging products instead of creating fixed-function hardware for each imaging application.
Q. What are the consumer benefits of the C64x in printing, scanning and copying applications?
A. Consumers will benefit from lower prices, leading performance and the latest feature sets and capabilities. End users will receive the performance that today is the exclusive domain of the most expensive, top-of-the-line models.
Q. What can the C55x do for digital still camera?
A. Increase resolution from 1-2M pixels today to 4-6M pixels. This 3X improvement in resolution will produce photo realistic images with no shot to shot delay. Battery life will increase from the equivalent of one roll of film to hundreds of pictures. Cameras will become more affordable.
Q. Can the C64x handle real-time video compression?
A. A single C64x CPU is capable of performing complete MPEG2 video compression. C64x also has outstanding performance on other compression algorithms. Key imaging benchmark results can be found on the C6000 web site at www.ti.com/sc/c6000/benchmarks
Return to top
Other Applications
Q. What can the C55x do for portable digital audio?
A. Battery life for credit card size players can increase from 20 hrs today on two AA batteries to over 200hrs. Future machines will deliver not only CD quality audio but music videos as well.
Q. What will these new cores do for motion and motor control applications?
A. TI's C24x family provides leadership solutions for these applications with an optimum mix of control and DSP functionality. TI's new C28x offers the industry's best performance for these types of applications. Over time, as performance and power consumption requirements evolve, future products with peripherals tailored for these applications are possible using TI's new C55x and C64x cores.
Q. Where can I find the performance benchmarks for the C64x and the C55x?
A. Check out the TI website for additional benchmarks across suites of applications. For the C64x, check out http://www.ti.com/sc/docs/products/dsp/c6000/benchmarks/index.htm and for the C55x check out http://www.ti.com/sc/docs/products/dsp/c5000/55xbench.htm for the latest results.
Return to top
CPU Technical Questions
TMS320C64x
Q. Where can I learn more about how the new instructions are implemented?
A. The TI website offers online training modules and technical documentation for the C64x. Check out http://www.ti.com/sc/twonewdsps for more information.
Q. What is the power consumption of the C64x?
A. Specific power numbers will be disclosed with chip announcements. Our power consumption for this class of performance will be significantly lower than that of general-purpose microprocessors operating at similar clock rates. Over time, you will see an array of C64x devices, including low-power versions, to address a broad range of performance intensive applications.
Q. What will the speed be of the initial C64x DSPs?
A. Initial versions to be announced this summer will range from 600-800MHz. The scalability of the C64x core combined with TI's advanced semiconductor process leadership should allow us to offer performance of over 1.1GHz in time.
Q. Can you outline how you achieve such a high clock rates for the C64X without extreme power?
A. The C64x uses an innovative logic, circuit, and design methodology that focuses on minimal wire lengths and low gate counts per clock to achieve phenomenal speed with power efficiency. This results in half the switching wires and transistors for the same amount of work completed compared to traditional approaches.
Q. How well does the compiler perform on the C64x?
A. Our latest compiler offers 35% higher performance and 30% smaller code size than our original compiler. A set of intrinsics, including data packing and unpacking will be in the Code Composer Studio release in April to support highly parallel quad 8-bit and dual 16-bit extensions. TI has more than 5 years of VLIW compiler experience resulting in best in Class compilers. Our compiler is developed internally through a tightly coupled relationship with our architecture team. Competitors who are just starting the VLIW or high performance journey will have a difficult time reaching our level of efficiency.
Q. Will existing C6000 customers need to re-write their code to take advantage of the instructions?
A. The April release of Code Composer Studio is the first version to support the C64x instruction extensions. All the optimization features enabled for C62x are also enabled for C64x. Automatic instruction selection of the C64x instruction extensions will occur in some but not all cases. Thus, recompiling existing C code for C64x will show some but not all of the performance speedup entitlement of the architecture. As always, all C6000 instructions (including the C64x extensions) are accessible from C with intrinsics, allowing the user to fully exploit the architecture features from C. Future versions of the C6000 compiler will more fully utilize the instruction extensions automatically with no changes to the C code.
Q. Where do you get 10X-performance improvement for the C64x?
A. The 10x improvement on the C64x relative to the C62x is an average speed-up due to a combination of clock rate and architecture improvements across a suite of DSP applications. Applications like Reed-Solomon error correction and motion estimation that can benefit from the new special purpose instructions enjoy even higher performance lifts.
Q. How many 32-bit general purpose registers are available on the C64x? How much larger is this than the C62x register size?
A. The C64x has doubled its register size from 32 to 64 32-bit general purpose registers available for the compiler to increase performance.
Q. Is the C64x code compatible with the C62x?
A. The C64x is object code compatible with the C62x. You do not even have to re-compile your code. C62x compiled code will run on the C64x, taking immediate advantage of the speed increase that the C64x core can offer the customer and their application.
Return to top
TMS320C55x
Q. Where can I get learn more about the new features of the C55x?
A. The TI website offers online technical training modules as well as complete technical documentation for the CPU core. Check out http://www.ti.com/sc/twonewdsps for more information.
Q. What is the most significant technical achievement for the C55x?
A. The C55x is the most energy efficient DSP. Battery operated devices can run longer and perform better. Not only is this a great story of low power design, but power management as well. Different sections of the C55x consume power only when needed. The rest of the time they are turned off. In addition, designers have the unique ability to tailor how combinations of sections are turned off and on, so power consumption can be optimized for different applications.
Q. Is the power consumption of the C55x core .05, .08 or .16mW/MIPS?
A. We offer two power-performance versions of the C55x core. Our ultra low power version of the C55x is powered by a .9v source and consumes .05MW/MIPS. Our traditional version of the C55x is powered by a 1.2v - 1.5V source and consumes .08mW/MIPS in our .13um process technology and .16mW/MIPS in our .15um process.
Q. Where do you get 1/6 the power consumption for a C55x vs C54x?
A. 100MHz C54x core consumes .32mW/MIPs. A 300MHz, .9v C55x core consumes .05mW/MIPS
Q. How does the C55x achieve 1/6 the power of the C54x?
A. The C55x design exhibits an unprecedented level of power management and an attention to detail in terms of low power that has never been implemented before in a DSP. The C55x is equipped with a Configurable Idle Domain capability as well as an extensive advanced power management technology. In addition to that, enhanced features, such as the 32-bit program bus, 32-bit EMIF, dual MAC, new general purpose registers, and new instructions mean that more work can be done in a given period of time than before. (i.e. The enhanced 32-bit program bus and EMIF mean that more memory can be accessed in a given instance; this decreases the amount of memory accesses.)
Q. What is the difference between the Configurable Idle Domain and the Advanced Power Management Capability?
A. The main difference is that the IDLE Domains are configurable and allow the user to control the power of 6 different regions of the device while the Advanced Power Management capabilities occur automatically and on a more detailed and granular level. Example: only the peripheral, memory array, or register being used at any given time contributes to power.
Q. When you say that the C55x is code compatible with the C54x, what does that really mean?
A. The C54x is source code compatible with the C55x. This means that existing C54x source code, when passed through the C55x assembler, will run on the C55x device with identical, bit-exact results. There is a 1-to-1 mapping of each C54x instruction to a C55x instruction that exhibits the same functionality. This means that the large C54x code base that exists today from TI, our customers, and 3rd parties, can be reused on the C55x, preserving the extensive software investments that have already been made.
Q. What steps have to be taken to run C54x code on the C55x?
A. Simply run the code through the C55x assembler. The C55x is a superset of the C54x. The reassembled code will run 2x faster just due to the clock rate alone. If the user would like to get the up 5x improvement, the can modify modules of their code to take advantage of the additional functional units at their leisure. For more detail information on the C55x compatibility, please view the "Field Support" portion of the P119 training, available at (http://tiu5.sc.ti.com).
Q. What are the acceptable widths for the "Variable Instruction Length" feature?
A. C55x instructions are 1, 2, 3, 4, 5, and 6 bytes long, This variability allows only the memory that is needed to be used.
Q. How are the variable length instructions handled by the C55x?
A. The C55x has a decoder that identifies the boundaries of instructions so that it can decode 8-, 16-, 24-, 32-, 40- and 48-bit instructions. This encoding method results in very high-density program code and optimal use of program memory.
Q. How is the C55x better at the control code shown in the webcast?
A. The C55x has an additional 16-bit ALU and 4 additional data registers that allow simple arithmetic and logical operations found in control applications to be performed. In addition, there are new addressing modes with the C55x and nearly every instruction can be executed conditionally which minimizes code branching, thus reducing overall code size.
Q. How does the C55x achieve its performance metrics?
A. The C55x has focused on increasing clock rate and cycle efficiency. Cycle efficiency was increased by: 1) additional functional units such as a second MAC (Multiply-Accumulate), 4 accumulators, and additional 16-bit ALU 2) additional and expanded busses 3) new instructions that increase parallelism capabilities. C55x clock rates extend up to 400MHz.
Q. How many busses does the C55x have?
A. The C55x has a total of 12 busses:
3 16-bit data read busses
2 16-bit data write busses
1 32-bit program read bus
6 24-bit address busses to correspond with the above data/prog. busses
Q. What is the performance of the initial C55X DSP?
A. We'll deliver production volumes in our .13um process with performance up to 800 MIPS (400MHz) at 1.2 -1.5v and 600 MIPS (300MHz) at .9v . This Spring we'll be sampling in our .15um process and deliver performance of 148 MIPS (74MHz) @ 0.9V and 400 MIPS (200MHz) @ 1.5V respectively.
Return to top
| 
