CDC7005 and CDCM7005 PLL Loop Bandwidth Calculator
CDC-CDCM7005-CALC
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Description & Features

Technical documentation

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CDC-CDCM7005-CALC:
CDC7005 and CDCM7005 PLL Loop Bandwidth Calculator (Labview)

Free



ACTIVE

Description

This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump current, and VCO gain (Hz/V). This is a software package that lets the Engineers enter a piecewise-linear noise model for the VCO (VCXO) and the reference clock source to predict the PLL output phase noise and hence calculate the phase jitter.

Features

The lab view based tool can:

  • Determine the PFD frequency automatically
  • Calculate loop bandwidth, Phase margin and Jitter peaking
  • Predict the PLL output Phase noise
  • Calculate Phase Jitter (rms)

Compatibility Issues

There are two versions of the tool available, depending on the program used:

  • For Labview version, download zip file SCAC059 (revision letter may be present depending on last update)
  • For Excel version, download zip file SCAC036 (revision letter may be present depending on last update)

Downloads can be accessed through the "Support Software" section of this folder.

Technical documentation
Datasheet (1)
Title Type Size (KB) Date
PDF 1841 03 Dec 2015
Design files (2)
Title Type Size (KB) Date
ZIP 31587 02 Feb 2006
ZIP 213 23 May 2003

TI Devices (2)

Part Number Name Product Family
CDC7005  High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO  Clocks & timing 
CDCM7005  High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO  Clocks & timing 

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