The CDC3S04 is a four-channel low-power sine-wave clock buffer. It can be used to buffer a single mastern clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter. Each output has its own clock request input which enables the dedicated clock output. These clock requests are active-high (can also be changed tobe active-low via I2C), and an output signal is generated that can be sent back to the master clock to request the clock (MCLK_REQ). MCKL_REQ is an open-source output and supports the wired-OR function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND or push-pull functionality via I2C.This evaluation module (EVM) is designed to demonstrate the electrical performance of theCDC3S04. For optimum performance, the board is equipped with 50-ohm SMA connectors and well controlled 50-ohm impedance microstrip transmission lines.
Kitting List
USB Cable
| Type | Title | Date | ||
|---|---|---|---|---|
| Certificate | CDC3S04EVM EU Declaration of Conformity (DoC) | 02 Jan 2019 | ||
| User guide | Quad Sine-Wave Clock Buffer Evaluation Board | 08 Mar 2010 |
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