The CDCLVP1102 is a high-performance, low additive phase noise clock buffer. It has a single universal input buffer that supports either single-ended or differential clock inputs, and feeds to two LVPECL outputs. The device also features on-chip bias generators that can provide the LVPECL common-mode voltage to the device inputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP1102. This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP1102 device functionalities. For optimum performance, the board is equipped with 50-W SMA connectors and well-controlled, 50-W impedance microstrip transmission lines.
| Type | Title | Date | ||
|---|---|---|---|---|
| Certificate | CDCLVP1102EVM EU Declaration of Conformity (DoC) | 02 Jan 2019 | ||
| EVM User's guide | CDCLVP1102EVM User's Guide | 09 Jul 2009 |
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