LMX1860-SEP evaluation module



The LMX1860-SEP evaluation module (EVM) is designed to evaluate the performance of the LMX1860-SEP, which is a four-output, ultra-low additive jitter radio-frequency (RF) buffer, divider and multiplier. This EVM can buffer RF clocking inputs up to 18GHz, multiply by two, by three or by four in the output range of 3.2GHz to 6.4GHz, and divide inputs by up to eight. A separate auxiliary clock divider is included for field-programmable gate arrays (FPGAs) and logic clocking. Each output includes a system reference (SYSREF) complement with picosecond precision and delay tuning capability. Multiple devices can be synchronized for wide clock distribution trees.

  • 18GHz buffer, up to 6.4GHz multiplier and divide by up to eight
  • -160dBc/Hz noise floor at 6GHz
  • Four RF output and SYSREF pairs
  • SYSREF generator with per-output picosecond precision delay tuning capability
  • Auxiliary divider for FPGA and logic with SYSREF
  • Supports multiple-device synchronization
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Evaluation board

LMX1860SEPEVM — LMX1860-SEP evaluation module

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Technical documentation

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Type Title Date
EVM User's guide LMX1860-SEP Evaluation Module User's Guide PDF | HTML 02 May 2024
Certificate LMX1860SEPEVM EU Declaration of Conformity (DoC) 04 Mar 2024

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