Scalable RTOS solution for single and multicore devices
TI-RTOS accelerates development schedules by eliminating the need to create basic system software functions from scratch. By providing essential system software components pre-tested and pre-integrated, TI-RTOS enables developers to focus on differentiating their application. For TI microprocessors and DSPs, TI-RTOS offers a real-time multitasking kernel TI-RTOS Kernel (formerly known as SYS/BIOS), device drivers, multicore communications, and TCP/IP networking . TI-RTOS components have a proven record of reliability in applications spaces such as industrial communications and control, wireless communications, and automotive.
To obtain TI-RTOS for SitaraTM Processors and DSPs
- Click “Get Software” button above for your applicable TI Processor Software Development Kit (SDK). These Processor SDKs contain additional examples, middleware, board support package, and compiler tools that are pretested with TI-RTOS on supported evaluation modules.
Licensing - TI-RTOS is provided with full source code and requires no up-front or runtime license fees. The multitasking kernel, device drivers, multicore communications, TCP/IP networking stack, and examples all use open source BSD-like licensing. This enables developers to easily pass on software to partners or sub-contractors without cumbersome licensing constraints. Unlike the GPL license, the BSD license does not impose requirements for developers to ship their entire application source code.
TI-RTOS offers the following components for TI Sitara microprocessors and TI DSPs:
TI-RTOS Kernel (formerly known as SYS/BIOS) provides deterministic preemptive multithreading and synchronization services, memory management, and interrupt handling.
|TI-RTOS Device Drivers
|TI-RTOS device drivers provide a common API interface layer abstracting differences across different processors.
|TI-RTOS Networking (formerly known as the NDK) provides an IPv4 and IPv6-compliant TCP/IP stack along with associated network applications such as DNS, HTTP, and DHCP.
|The TI-RTOS IPC provides efficient interprocessor communication in multicore devices.
|TI-RTOS Instrumentation allows developers to include debug instrumentation in their application that enables run-time behavior, including context-switching, to be displayed by system-level analysis tools.
TI-RTOS Kernel Overview
TI-RTOS Kernel is a deterministic, preemptive, multitasking kernel that enables developers to create sophisticated applications without compromising real-time deadlines. The kernel services are summarized in the table below:
|Cache configuration and management
|User-configurable tracing including asserts for parameter and state checking
|Define, raise, and check error-handlers
Wait on any combination of multiple RTOS or custom events
|Binary mutex with priority inheritance
|Fast, deterministic fixed-size buffer pools
|Variable-sized dynamic heaps
Variable-sized, deterministic dynamic heaps based on multiple buffer pools
|Hardware Interrupts (HWI)
Interface from hardware interrupts to the RTOS
Low-overhead logging and print statements
|Synchronized data exchange between tasks
Memory allocation interface
|Software Interrupts (SWI)
|Lightweight preemptible threads that use the program stack but cannot yield
General system functions such as abort, exit, and system printf
|Independent threads of execution that can yield the processor
|Interface to hardware timers
32- and 64-bit timestamping services
TI-RTOS Kernel Multicore Support
TI-RTOS fully supports TI's multicore ARM and DSP solutions. The TI-RTOS Kernel can run on ARM Cortex A, ARM Cortex M, and DSP cores, providing a uniform set of OS APIs across all cores. TI-RTOS Kernel also offers shared image and SMP support for appropriate devices. The associated IPC Package provides an extensive set of multicore communication mechanisms that simplify development of distributed applications and leverage any hardware mutual exclusion features for maximum performance. The IPC services are available for both TI-RTOS and Linux, enabling developers to use Linux on the ARM Cortex A core and TI-RTOS on DSP and ARM Cortex M cores if desired:
|IPC Services Description
Multicore/processor-safe shared memory implementation of HeapBuf
Multicore/processor-safe shared memory implementation of HeapMultiBuf
|Atomic linked lists
|Multiprocessor atomic linked lists
|Transparent, variable-length messages
|Enables location of IPC objects in multicore/processor topologies
|Low-latency asynchronous interrupt to another processor
|Enables definition of shared pointers between different processors/cores
|Read/write or buffer streaming interface to peripheral drivers
OS-aware Debug and Analysis Tools
In conjunction with Code Composer Studio (CCS), TI-RTOS Kernel provides several tools to aid debugging and optimization of multithreaded applications. The Run-time Object Viewer (ROV) enables a developer to check the status of OS objects such as tasks, mailboxes, and semaphores, including whether a task is ready, running or blocked; which tasks are blocked on an IPC; and whether tasks have exceeded their stack limits. The RTOS Analyzer that captures behavior in real-time and can display the thread execution and switching sequence, thread and system CPU load, OS events, and user-defined log information.
TI-RTOS Networking Overview
TI-RTOS Networking - formerly known as the Network Developer Kit (NDK) - combines a dual mode IPv4/IPv6 stack with some network applications. TI-RTOS Networking support is available for both Ethernet-enabled MCU, MPUs, and DSPs. TI-RTOS Networking includes:
- Core TCP/IP protocol stack: Dual-mode IPv6/IPv4 stack in both source and binary, including VLAN packet priority-marking, TCP, UDP, ICMP, IGMP, IP, and ARP
- Network applications: HTTP, TELNET, TFTP, SNTP, DNS, DHCP (IPv4 only) client and server
- Serial/cellular modem support: PPP and PPPoe
- Application Programming interfaces: BSD Sockets, zero-copy sockets, and support for raw Ethernet